Information processing apparatus, method for controlling information processing apparatus, and storage medium

ABSTRACT

Even when activation processing of one of communication units is not completed by power supplied to a plurality of controllers, the present invention allows a reset signal output to each of the controllers to be released, thereby reducing an activation time of an entire system.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an information processing apparatus, amethod for controlling an information processing apparatus, and astorage medium.

2. Description of the Related Art

In recent years, for example, Peripheral Component Interconnect Express(PCI Express) (registered trademark) (hereinafter referred to as PCIe))has been widely used by information processing apparatuses includingpersonal computers (PCs) as a communication standard for datacommunication requiring a wide bandwidth.

The PCIe standard defines the following specification. Within 100milliseconds (ms) since a reset is released after power is supplied to adevice, the device should complete initialization processing thereof,and start a link training sequence. Then, the device should completeprocessing for establishing a link to achieve link-up, thereby shiftingto a state capable of receiving a configuration request.

Further, on the other hand, it has been becoming common to use a devicehaving an arbitrarily configurable logical circuit, such as afield-programmable gate array (FPGA), as the PCIe device. The use of theFPGA as the PCIe device requires completion of configuration of the FPGAincluding a PCIe control unit, which will serve as an endpoint, beforethe link training sequence starts after the power is supplied to thedevice.

Generally, the configuration of the FPGA takes a different time untilthe completion thereof depending on a size of circuit information. Thismeans that it also takes a different time until the completion of theinitialization processing and the start of the link training sequencedepending on the size of the circuit information.

When the time taken for the initializing processing varies for eachdevice supposed to communicate or the time taken until the start of thelink training sequence varies depending on the size of the circuitinformation of the FPGA in this manner, the following problem arises.This variation may raise such a problem that one of devices cannotcomplete the initialization processing thereof, making it impossible tosecure a time required for the link training sequence within the timeperiod specified by the standard.

Therefore, the following method is proposed to solve the problem ofbeing unable to achieve the link-up between the communication devices.For example, there is proposed a method that performs control of, withrespect to power supply to a PCIe communication device, delaying thepower supply so as to supply power after receiving a notificationindicating completion of activation processing of a PCIe communicationdevice for which the initializing processing takes a long time (JapanesePatent Application Laid-Open No. 2012-022477).

This method performs the control of delaying the power supply so as tosynchronize timings when the PCIe communication devices start the linktraining sequence, thereby ensuring that the link-up can be achieved.

However, the above-described method results in an increase in anactivation time in terms of activation of the entire system because thismethod delays the timing of supplying the power to the PCIecommunication device. The information processing apparatuses are desiredto be able to be booted up in a shorter time after being powered on, sothat the increase in the activation time of the entire system isundesirable.

Further, in a system including a plurality of PCIe communication devicesconnected to one another, no power is supplied to the PCIe communicationdevices if some abnormality has occurred and even only one PCIecommunication device has failed to normally complete the activationprocessing thereof. Therefore, the system ends up in a state incapableof connecting to all of the PCIe communication devices.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, an informationprocessing apparatus as one exemplary embodiment of the presentinvention includes the following configuration.

An information processing apparatus, in which a first controllerincluding a first communication unit and a second controller including asecond communication unit perform processing in communication with eachother, includes a signal generation unit configured to generate a thirdsignal from a first signal indicating that communication of the secondcommunication unit can be established by power supplied from a powersource unit and a second signal indicating that the communication of thesecond communication unit cannot be established by the power suppliedfrom the power source unit, and a reset unit configured to release areset signal output to the first controller or the second controlleraccording to reception of the third signal.

Further features of the present invention will become apparent from thefollowing description of exemplary embodiments with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of an informationprocessing apparatus.

FIG. 2 is a block diagram illustrating a configuration of a Ready signalgeneration unit.

FIGS. 3A, 3B, and 3C are flowcharts illustrating a method forcontrolling the information processing apparatus.

FIGS. 4A and 4B are timing diagrams illustrating an operationillustrated in FIG. 1.

FIG. 5 is a block diagram illustrating a configuration of the Readysignal generation unit.

FIG. 6 is a flowchart illustrating a method for controlling theinformation processing apparatus.

DESCRIPTION OF THE EMBODIMENTS

Next, exemplary embodiments of the present invention will be describedwith reference to the drawings.

<Description of System Configuration>

FIG. 1 is a block diagram illustrating a configuration of an informationprocessing apparatus indicating a first exemplary embodiment. In thepresent exemplary embodiment, assume that possible types of theinformation processing apparatus include a printing apparatus, an imageforming apparatus, and a multifunction image forming apparatus.

In FIG. 1, an information processing apparatus 150 includes a maincontrol unit 100, a sub-control unit 140, a function extension unit 170,a power supply unit 130, a power source reset control unit 160, and apower source unit 105. The main control unit 100 will be referred to asa first controller, and the sub-control unit 140 and the functionextension unit 170 will be each referred to as a second controller.

The main control unit 100 includes a read only memory (ROM) 101, acentral processing unit (CPU) 102, a random access memory (RAM) 103, aPCIe control unit 104, and a hard disk drive (HDD) 106. The ROM 101contains a boot program (a Basic Input/Output System (BIOS)), anoperating system (OS), and an application program. The power source unit105 converts direct-current (DC) power 131 supplied from the powersupply unit 130 into an appropriate voltage required by the main controlunit 100 and the sub-control unit 140. Then, upon stabilization of theconverted voltage, the power source unit 105 notifies the power sourcereset control unit 160 of that via a Power Good (PGOOD) signal 161. Whenthe power source unit 105 supplies power 133 to the main control unit100, and the power source reset control unit 160 releases a reset signal163, the CPU 102 reads out the boot program from the ROM 101 and startsan operation. At this time, the power source reset control unit 160releases the reset signal 163 output to the main control unit 100, thesub-control unit 140, or the function extension unit 170 according toreception of a READY signal, which is a third signal.

The RAM 103 temporarily stores data when the CPU 102 executes a program,and data read out from the HDD 106. The HDD 106 stores data processed orto be processed on the program that runs by the CPU 102.

The PCIe control unit 104 is connected to a PCIe control unit 142 of thesub-control unit 140 via a PCIe bus 144, and provides and receives datato and from the sub-control unit 140. Further, the PCIe control unit 104is connected to a PCIe control unit 112 of an FPGA 110 via a PCIe bus120, and provides and receives data to and from the FPGA 110. The PCIecontrol unit 142 will be referred to as a second communication unit.

The PCIe control unit 104 is brought into a state capable of confirminga physical connection by link training without intervention of the CPU102, when the power 133 is supplied from the power source unit 105 tothe main control unit 100 and the reset signal 163 is released by thepower source reset control unit 160.

The sub-control unit 140 includes a CPU 141, the PCIe control unit 142,and a RAM 143. The RAM 143 temporarily stores a boot program, and datawhen the CPU 141 executes a program. The PCIe control unit 142 isbrought into the state capable of confirming a physical connection bythe link training without intervention of the CPU 141, when the power133 is supplied from the power source unit 105 to the sub-control unit140 and the reset signal 163 is released by the power source resetcontrol unit 160.

The PCIe control unit 142 receives data of the boot program of the CPU141 from the PCIe control unit 104 of the main control unit 100 to thendevelop the received data into the RAM 143, by which the CPU 141 startsan operation. The function extension unit 170 includes the FPGA 110, aROM 114, a power source unit 115, and a Ready signal generation unit116.

The function extension unit 170 is a detachably attachable unitelectrically connected to the information processing apparatus 150 via acard edge connector (not illustrated), a general-purpose connector (notillustrated), a general-purpose cable (not illustrated), or the like. Inthe present exemplary embodiment, the function extension unit 170 isdescribed as the detachably attachable unit by way of example, but thepresent invention can also be applied to the function extension unit 170that is not detachably attachable. If the function extension unit 170 iselectrically connected to the information processing apparatus 150, thefunction extension unit 170 outputs a function extension unit detectionsignal 171.

The function extension unit detection signal 171 is, for example,connected to power 134 by a pull-up connection via a resistor (notillustrated) in the function extension unit 170. Then, the functionextension unit 170 may be configured in such a manner that the functionextension unit detection signal 171 is output if the function extensionunit 170 is electrically connected to the information processingapparatus 150. Further, the function extension unit 170 may beconfigured in such a manner that a CPU (not illustrated) or the like inthe function extension unit 170 outputs the function extension unitdetection signal 171.

If the function extension unit 170 is not mounted, the functionextension unit detection signal 171 is not output but the informationprocessing apparatus 150 is operable in the configuration including themain control unit 100, the sub-control unit 140, the power source unit105, the power supply unit 130, and the power source reset control unit160.

The FPGA 110 includes a user logic unit 111, the PCIe control unit 112,and a configuration unit 113. The user logic unit 111, which functionsas a user logic unit for the FPGA 110, is a circuit unit rewritable bythe configuration unit 113. The PCIe control unit 112 will be referredto as the second communication unit.

The PCIe control unit 112 is connected to the PCIe control unit 104 ofthe main control unit 100 via the PCIe bus 120, and provides andreceives the data to and from the main control unit 100. In a case wherethe PCIe control unit 112 is a hard macro of the FPGA 110, setting thePCIe control unit 112 to initial settings thereof should be completed bythe configuration unit 113 to bring the PCIe control unit 112 into thestate capable of confirming a physical connection by the link training.

The power source unit 115 converts DC power 132 supplied from the powersupply unit 130 into an appropriate voltage required by the FPGA 110 andthe ROM 114, and notifies the Ready signal generation unit 116 of aPGOOD signal 122 upon stabilization of the converted voltage.

The configuration unit 113 configures the user logic unit 111 and setsthe user logic unit 111 and the PCIe control unit 112 to theirrespective initial settings according to information stored in the ROM114 upon supply of the power 134 from the power source unit 115 to theFPGA 110. The configuration unit 113 configures the user logic unit 111and sets the user logic unit 111 and the PCIe control unit 112 to theirrespective initial settings without waiting for the release of the resetsignal 163.

Further, upon completing the configuration based on the information readfrom the ROM 114, the configuration unit 113 notifies the Ready signalgeneration unit 116 of this completion via a CONFIG_DONE signal 121.

The ROM 114 stores initial setting information of the PCIe control unit112 (hereinafter referred to as interface information), configurationinformation and initial setting information of the user logic unit 111(hereinafter referred to as core information), and the like.

The Ready signal generation unit 116 generates a Ready signal 162 fromstates of the CONFIG_DONE signal 121 and the PGOOD signal 122 by amethod that will be described below, and notifies the power source resetcontrol unit 160 of the Ready signal 162.

The power source reset control unit 160 releases the reset signal 163upon being notified of both the PGOOD signal 161 from the power sourceunit 105 and the Ready signal 162 from the Ready signal generation unit116, when the function extension unit detection signal 171 is output.

The power source reset control unit 160 releases the reset signal 163upon being notified of only the PGOOD signal 161 from the power sourceunit 105, when the function extension unit detection signal 171 is notoutput.

The power supply unit 130 converts power supplied from analternating-current (AC) power source (not illustrated) from AC power toDC power, and supplies the DC power 131 and the DC power 132 to thepower source unit 105 and the power source unit 115, respectively.

FIG. 2 is a block diagram illustrating a configuration of the Readysignal generation unit 116 illustrated in FIG. 1.

In FIG. 2, the Ready signal generation unit 116 includes a timer unit200, an AND gate 201, and an OR gate 202. The AND gate 201 generates asignal (a first signal) acquired by performing an AND operation on theCONFIG_DONE signal 121 and the PGOOD signal 122, and outputs thegenerated signal to the OR gate 202.

The timer unit 200 measures a time (a predetermined time) elapsed sincethe start of the supply of the power 134 to the Ready signal generationunit 116, and outputs a signal to the OR gate 202 after thepredetermined time has elapsed. The OR gate 202 outputs a signalacquired by performing an OR operation on the signal from the AND gate201 and the signal from the timer unit 200 (a second signal) to thepower source reset control unit 160 as the Ready signal 162 (a thirdsignal). The Ready signal generation unit 116 is assumed to beconfigured in such a manner that the above-described predetermined timecan be determined variably according to a resource of the functionextension unit 170.

FIGS. 3A, 3B, and 3C are flowcharts illustrating a method forcontrolling the information processing apparatus 150 according to thepresent exemplary embodiment. In particular, FIG. 3A illustrates anexample of activation processing of the function extension unit 170 inthe information processing apparatus 150.

First, when a system power source (not illustrated) is turned on, thepower source unit 115 supplies the power 134 to the FPGA 110. In stepS301, the configuration unit 113 reads out the interface informationfrom the RAM 114. In step S302, the configuration unit 113 sets the PCIecontrol unit 112 to the initial settings thereof.

Upon completing setting the PCIe control unit 112 to the initialsettings thereof, in step S303, the configuration unit 113 outputs theCONFIG_DONE signal 121 for notifying the Ready signal generation unit116 that the configuration is completed (READY notification). At thisstage, the PCIe control unit 112 is brought into the state capable ofconfirming a physical connection by the link training.

Next, in step S304, the PCIe control unit 112 and the PCIe control unit104 carry out the link training with each other, thereby establishing aphysical connection therebetween. If the PCIe control unit 112determines that the link training with each other has been completednormally in step S305 (YES in step S305), in step S306, the PCIe controlunit 112 on the FPGA 110 side responds to a request from the PCIecontrol unit 104 on the main control unit 100 side. For example, thePCIe control unit 112 transmits a vendor identification (ID) and/or adevice ID set to their respective initial settings in step S302 to themain control unit 100 via the PCIe bus 120 in response to a request totransmit the vendor ID and/or the device ID from the main control unit100.

If the PCIe control unit 112 determines that the link training with eachother has not been completed normally in step S304 (NO in step S305),the activation processing ends without a further operation to beperformed.

FIG. 3B is an example of activation processing of the main control unit100 in the information processing apparatus 150 illustrated in FIG. 1.

If the reset signal 163 is released by the power source reset controlunit 160 (YES in step S310), in step S311, the PCIe control unit 104 isinitialized into the state capable of confirming a physical connectionby the link training without the intervention of the CPU 102. Then, instep S312, the PCIe control unit 104, and each of the PCIe control unit112 and the PCIe control unit 142 carry out the link training with eachother, thereby establishing the physical connection therebetween.

After that, in step S313, the CPU 102 reads out the BIOS from the ROM101 and starts booting up the main control unit 100. During thisprocessing, in step S314, the CPU 102 transmits a request for searchingfor a device connected at a location beyond each of the PCIe bus 120 andthe PCIe bus 144 via the PCIe control unit 104.

If the link training with each other has been completed normally in stepS312, the PCIe control unit 112 of the function extension unit 170 andthe PCIe control unit 142 of the sub-control unit 140 respond to therequest output from the PCIe control unit 104 on the main control unit100 side. This response to the request allows the main control unit 100to recognize the sub-control unit 140 and the function extension unit170 as PCIe devices.

If the PCIe control unit 104 determines that the response to the requestis transmitted from all of the PCIe control units 112 and 142 (YES instep S315), the main control unit 100 determines that the activation hasbeen completed normally. Then, in step S316, the main control unit 100starts a normal operation. Then, the activation processing ends.

Next, if the response to the request is not transmitted from all of thePCIe control units 112 and 142 (NO in step S315), in step S317, the maincontrol unit 110 determines whether the response to the request istransmitted from the PCIe control unit 142 of the sub-control unit 140.

If the response to the request is transmitted from the PCIe control unit142 but is not transmitted from the PCIe control unit 112 (YES in stepS317), in step S318, the main control unit 100 starts an operationtogether with the sub-control unit 140 as an operation of reducedprocessing. Then, the activation processing ends.

If the PCIe control unit 104 determines that the response to the requestis not transmitted from the PCIe control unit 142 (NO in step S317), instep S319, the main control unit 100 presents a display indicating thatan activation error has occurred on a display unit (not illustrated)included in an operation unit (not illustrated). Then, the activationprocessing ends.

This processing allows a user to confirm that the information processingapparatus 150 cannot detect a specific device (the function extensionunit 170 in the present exemplary embodiment) and thus is activated inreduced operation, thereby quickly taking measures after that, such asreplacing the device.

FIG. 3C illustrates an example of activation processing of the functionextension unit 170 in the information processing apparatus 150 accordingto the present exemplary embodiment.

If the reset signal 163 is released by the power source reset controlunit 160 (YES in step S320), in step S321, the PCIe control unit 142 isinitialized into the state capable of confirming a physical connectionby the link training without the intervention of the CPU 141. Then, instep S322, the PCIe control unit 142 and the PCIe control unit 104 carryout the link training with each other, thereby establishing the physicalconnection therebetween.

If the PCIe control unit 142 determines that the link training with eachother has been completed normally in step S322 (YES in step S323), instep S324, the PCIe control unit 142 of the sub-control unit 140responds to the request from the PCIe control unit 104 on the maincontrol unit 100 side. Then, the activation processing ends.

On the other hand, if the PCIe control unit 142 determines that the linktraining with each other has not been completed normally in step S322(NO in step S323), the activation processing ends without a furtheroperation to be performed.

FIGS. 4A and 4B are timing diagrams illustrating the operationillustrated in FIG. 1.

In particular, FIG. 4A is a timing diagram illustrating the operationuntil the main control unit 100, the sub-control unit 140, and thefunction extension unit 170 illustrated in FIG. 1 are activatednormally, and the connection via each of the PCIe bus 144 and the PCIebus 120 is established.

First, when the system power source (not illustrated) is turned on, thepower source unit 105 converts the voltage of the power 131 into theappropriate voltage, and notifies the power source reset control unit160 of the PGOOD signal 161 upon the stabilization of the convertedvoltage (time t=T1). Further, the power source unit 115 converts thevoltage of the power 132 into the appropriate voltage, and notifies theReady signal generation unit 116 of the PGOOD signal 122 upon thestabilization of the converted voltage (time t=T2).

Next, the configuration unit 113 notifies the Ready signal generationunit 116 of the CONFIG_DONE signal 121 upon completing the configuration(time t=T3).

The Ready signal generation unit 116 notifies the power source resetcontrol unit 160 of the Ready signal 162 upon being notified of both thePGOOD signal 122 and the CONFIG_DONE signal 121 (time t=T3).

The power source reset control unit 160 releases the reset signal 163upon being notified of both the PGOOD signal 161 and the Ready signal162 (time t=T4).

At time t=T5, the PCIe control unit 104, and each of the PCIe controlunit 112 and the PCIe control unit 142 start the link training with eachother, thereby establishing the physical connection therebetween.

At time t=T6, the CPU 102 transmits the request for searching for adevice connected at a location beyond the PCIe bus 120 and the PCIe bus144 via the PCIe control unit 104. By responding to this request, thePCIe control unit 112 and the PCIe control unit 142 allow the maincontrol unit 100 to recognize the sub-control unit 140 and the functionextension unit 170 as the PCIe devices.

FIG. 4B is a timing diagram illustrating the operation until theconnection via the PCIe bus 144 is established when the main controlunit 100 and the sub-control unit 140 illustrated in FIG. 1 areactivated normally but the function extension unit 170 illustrated inFIG. 1 has failed to be activated normally because some abnormality hasoccurred therein.

First, when the system power source (not illustrated) is turned on, thepower source unit 105 converts the voltage of the power 131 into theappropriate voltage, and notifies the power source reset control unit160 of the PGOOD signal 161 upon the stabilization of the convertedvoltage (time t=T1). Further, the power source unit 115 converts thevoltage of the power 132 into the appropriate voltage, and notifies theReady signal generation unit 116 of the PGOOD signal 122 upon thestabilization of the converted voltage (time t=T2).

Next, the timer unit 200 measures the time since the start of the supplyof the power 134 to the Ready signal generation unit 116, and the Readysignal generation unit 116 forcibly outputs the signal as the Readysignal 162 after the predetermined time has elapsed (time t=T7). Thepower source reset control unit 160 releases the reset signal 163 uponbeing notified of both the PGOOD signal 161 and the Ready signal 162(time t=T8).

At time t=T9, the PCIe control unit 104 and the PCIe control unit 142start the link training with each other, thereby establishing thephysical connection therebetween.

At time t=T10, the CPU 102 transmits the request for searching for adevice connected at a location beyond the PCIe bus 144 via the PCIecontrol unit 104. By responding to this request, the PCIe control unit142 allows the main control unit 100 to recognize the sub-control unit140 as the PCIe device.

According to the above-described exemplary embodiment, when theinformation processing apparatus 150 is activated normally, it can beensured that the function extension unit 170 is detected as the PCIedevice at the time of the processing for searching for a PCIe device,which is performed by the CPU 102 of the main control unit 100. Further,at the same time, the activation time of the entire system can beminimized.

On the other hand, even when an abnormality has occurred in the functionextension unit 170, the information processing apparatus 150 canpartially operate as the reduced operation.

Next, a second exemplary embodiment will be described with reference tothe drawings. Descriptions will be omitted below regarding the drawingsand the drawings of the flowcharts already described in the firstexemplary embodiment. A difference between the second exemplaryembodiment and the first exemplary embodiment is the block diagram ofthe Ready signal generation unit 116 illustrated in FIG. 2. Morespecifically, the second exemplary embodiment is different from thefirst exemplary embodiment in terms of the method for outputting theReady signal 162 from the states of the CONFIG_DONE signal 121 and thePGOOD signal 122.

FIG. 5 is a block diagram illustrating a configuration of the Readysignal generation unit 116 indicating the present exemplary embodiment.

In FIG. 5, the Ready signal generation unit 116 includes a CPU 500. TheCONFIG_DONE signal 121 and the PGOOD signal 122 are input, and the CPU500 determines whether to output the Ready signal 162 from the statesthereof by a method that will be described below. The CPU 500 storesinformation (an abnormality flag) indicating that the function extensionunit 170, which is the second controller, is in an abnormal state, ifthe Ready signal generation unit 116 is kept in such a state that thefirst signal is not input even after a predetermined time has elapsed,every time the power 134 is supplied from the power source unit 115.

FIG. 6 is a flowchart illustrating a method for controlling theinformation processing apparatus 150 according to the present exemplaryembodiment. The present example is an example of processing in which theCPU 500 determines whether to output the Ready signal 162.

After the power 134 is supplied to the Ready signal generation unit 116,in step S601, the CPU 500 determines whether the abnormality flag israised. If the CPU 500 determines that the abnormality flag is raised(YES in step S601), the processing proceeds to step S604.

On the other hand, if the CPU 500 determines that the abnormality flagis not raised (NO in step S601), in step S602, the CPU 500 determineswhether the PGOOD signal 122 has been output.

If the CPU 500 determines that the PGOOD signal 122 has been output instep S602 (YES in step S602), in step S603, the CPU 500 determineswhether the CONFIG_DONE signal 121 has been output. If the CPU 500determines that the PGOOD signal 122 has not been output in step S602(NO in step S602), the processing proceeds to step S605.

If the CPU 500 determines that the CONFIG_DONE signal 121 has beenoutput in step S603 (YES in step S603), the processing proceeds to stepS604. If the CPU 500 determines that the CONFIG_DONE signal 121 has notbeen output in step S603 (NO in step S603), the processing proceeds tostep S605.

In step S604, the CPU 500 outputs the Ready signal 162. Then, theprocessing ends.

On the other hand, in step S605, the CPU 500 determines whether thepredetermined time t T7 illustrated in FIG. 4 has elapsed after thesupply of the power 134. If the CPU 500 determines that thepredetermined time has elapsed (YES in step S605), the processingproceeds to step S606.

If the CPU 500 determines that the predetermined time t=T7 has notelapsed after the supply of the power 134 in step S605 (NO in stepS605), the processing proceeds to step S602.

In step S606, the CPU 500 increments a count that indicates how manytimes an abnormality has occurred at the time of the activation. In stepS607, the CPU 500 determines whether the number of occurrences ofabnormality is N time(s) or more. This N is a number of one or larger.If the CPU 500 determines that the number of occurrences of abnormalityis N time(s) or more in step S607 (YES in step S607), the processingproceeds to step S608. If the CPU 500 determines that the number ofoccurrences of abnormality is not N time(s) or more in step S607 (NO instep S607), the processing proceeds to step S604. In step S608, the CPU500 raises the abnormality flag. Then, the processing proceeds to stepS604.

According to the above-described exemplary embodiment, when theinformation processing apparatus 150 is activated normally, it can beensured that the function extension unit 170 is detected as the PCIedevice at the time of the processing for searching for a PCIe device,which is performed by the CPU 102 of the main control unit 100. Further,at the same time, the activation time of the entire system can beminimized.

Further, if an abnormality has occurred in the function extension unit170, the present exemplary embodiment leads to waiting until the timet=T7 has elapsed when an abnormality has occurred for the first time,regarding the activation time taken to make the information processingapparatus 150 partially operable as the reduced operation.

On the other hand, when and after an abnormality has occurred N-th time,the processing proceeds from step S601 to step S604 without waitinguntil the time=T7 has elapsed, so that the activation time can beminimized.

The present invention can also be realized by the following processing.A program capable of realizing one or more function(s) of theabove-described exemplary embodiments is supplied to a system or anapparatus via a network or a storage medium. Then, one or moreprocessor(s) in a computer of this system or apparatus read(s) out theprogram and execute(s) the program. Further, the present invention canalso be realized by a circuit capable of realizing one or morefunction(s) (for example, an application specific integrated circuit(ASIC)).

OTHER EMBODIMENTS

Embodiments of the present invention can also be realized by a computerof a system or apparatus that reads out and executes computer executableinstructions recorded on a storage medium (e.g., non-transitorycomputer-readable storage medium) to perform the functions of one ormore of the above-described embodiment(s) of the present invention, andby a method performed by the computer of the system or apparatus by, forexample, reading out and executing the computer executable instructionsfrom the storage medium to perform the functions of one or more of theabove-described embodiment(s). The computer may comprise one or more ofa central processing unit (CPU), micro processing unit (MPU), or othercircuitry, and may include a network of separate computers or separatecomputer processors. The computer executable instructions may beprovided to the computer, for example, from a network or the storagemedium. The storage medium may include, for example, one or more of ahard disk, a random-access memory (RAM), a read only memory (ROM), astorage of distributed computing systems, an optical disk (such as acompact disc (CD), digital versatile disc (DVD), or Blu-ray Disc (BD)™),a flash memory device, a memory card, and the like.

While the present invention has been described with reference toexemplary embodiments, it is to be understood that the invention is notlimited to the disclosed exemplary embodiments. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all such modifications and equivalent structures andfunctions.

This application claims the benefit of Japanese Patent Application No.2015-047098, filed Mar. 10, 2015, which is hereby incorporated byreference herein in its entirety.

What is claimed is:
 1. An information processing apparatus in which afirst controller including a first communication unit and a secondcontroller including a second communication unit perform processing incommunication with each other, the information processing apparatuscomprising: a signal generation unit configured to generate a thirdsignal from a first signal indicating that communication of the secondcommunication unit can be established by power supplied from a powersource unit, and a second signal indicating that the communication ofthe second communication unit cannot be established by the powersupplied from the power source unit; and a reset unit configured torelease a reset signal output to the first controller or the secondcontroller according to reception of the third signal.
 2. Theinformation processing apparatus according to claim 1, wherein thesignal generation unit includes a timer configured to output the secondsignal if a time for which the first signal is not input exceeds apredetermined time.
 3. The information processing apparatus according toclaim 2, wherein the predetermined time is determined according to aresource included in the second controller.
 4. The informationprocessing apparatus according to claim 1, further comprising a storageunit configured to store information indicating that the secondcontroller is in an abnormal state if the information processingapparatus is kept in such a state that the first signal is not inputeven after a predetermined time has elapsed, every time the power issupplied from the power source unit, wherein, when the power is suppliedfrom the power source unit, the signal generation unit confirms that thestorage unit stores the information indicating that the secondcontroller is in the abnormal state, and outputs the third signalwithout waiting until the predetermined time has elapsed.
 5. Theinformation processing apparatus according to claim 1, wherein the firstcontroller includes a control unit configured to confirm that the secondcommunication unit does not respond, and cause execution ofpredetermined reduced processing that does not include processing by thesecond controller, after the reset signal is input.
 6. The informationprocessing apparatus according to claim 1, wherein the second controllerincludes a user logic unit for an FPGA, and a configuration unit.
 7. Theinformation processing apparatus according to claim 1, wherein possibletypes of the information processing apparatus include a printingapparatus, an image forming apparatus, and a multifunction image formingapparatus.
 8. A method for controlling an information processingapparatus in which a first controller including a first communicationunit and a second controller including a second communication unitperform processing in communication with each other, the methodcomprising: generating a third signal from a first signal indicatingthat communication of the second communication unit can be establishedby power supplied from a power source unit, and a second signalindicating that the communication of the second communication unitcannot be established by the power supplied from the power source unit;and releasing a reset signal output to the first controller or thesecond controller according to reception of the third signal.
 9. Acomputer-readable storage medium storing a program for causing acomputer to perform a method for controlling an information processingapparatus in which a first controller including a first communicationunit and a second controller including a second communication unitperform processing in communication with each other, the programcomprising: a code for generating a third signal from a first signalindicating that communication of the second communication unit can beestablished by power supplied from a power source unit, and a secondsignal indicating that the communication of the second communicationunit cannot be established by the power supplied from the power sourceunit; and a code for releasing a reset signal output to the firstcontroller or the second controller according to reception of the thirdsignal.